ARAIAug 4, 2025

Revisit Choice Network for Synthesis and Technology Mapping

arXiv:2508.14068v1h-index: 42025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
Originality Incremental advance
AI Analysis

This work addresses structural bias issues in Boolean optimization and technology mapping for circuit design, offering incremental improvements over existing techniques.

The paper tackles the problem of constructing high-quality Boolean choice networks for technology mapping by introducing Cristal, a methodology that uses structural mutation and priority-ranking selection to generate fewer but better choices, resulting in average reductions of 3.85%/8.35% in area/delay and a 63.77% runtime reduction compared to state-of-the-art methods.

Choice network construction is a critical technique for alleviating structural bias issues in Boolean optimization, equivalence checking, and technology mapping. Previous works on lossless synthesis utilize independent optimization to generate multiple snapshots, and use simulation and SAT solvers to identify functionally equivalent nodes. These nodes are then merged into a subject graph with choice nodes. However, such methods often neglect the quality of these choices, raising the question of whether they truly contribute to effective technology mapping. This paper introduces Cristal, a novel methodology and framework for constructing Boolean choice networks. Specifically, Cristal introduces a new flow of choice network-based synthesis and mapping, including representative logic cone search, structural mutation for generating diverse choice structures via equality saturation, and priority-ranking choice selection along with choice network construction and validation. Through these techniques, Cristal constructs fewer but higher-quality choices. Our experimental results demonstrate that Cristal outperforms the state-of-the-art Boolean choice network construction implemented in ABC in the post-mapping stage, achieving average reductions of 3.85%/8.35% (area/delay) in delay-oriented mode, 0.11%/2.74% in area-oriented mode, and a 63.77% runtime reduction on large-scale cases across a diverse set of combinational circuits from the IWLS 2005, ISCAS'89, and EPFL benchmark suites.

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