QuadINR: Hardware-Efficient Implicit Neural Representations Through Quadratic Activation
This addresses the problem of high hardware overhead in INRs for researchers and engineers in signal processing and embedded systems, offering a significant but incremental improvement over existing approaches.
The paper tackles the hardware inefficiency of Implicit Neural Representations (INRs) by introducing QuadINR, which uses piecewise quadratic activation functions to achieve up to 2.06dB PSNR improvement while reducing area by up to 97% and power by up to 97% compared to prior methods.
Implicit Neural Representations (INRs) encode discrete signals continuously while addressing spectral bias through activation functions (AFs). Previous approaches mitigate this bias by employing complex AFs, which often incur significant hardware overhead. To tackle this challenge, we introduce QuadINR, a hardware-efficient INR that utilizes piecewise quadratic AFs to achieve superior performance with dramatic reductions in hardware consumption. The quadratic functions encompass rich harmonic content in their Fourier series, delivering enhanced expressivity for high-frequency signals, as verified through Neural Tangent Kernel (NTK) analysis. We develop a unified $N$-stage pipeline framework that facilitates efficient hardware implementation of various AFs in INRs. We demonstrate FPGA implementations on the VCU128 platform and an ASIC implementation in a 28nm process. Experiments across images and videos show that QuadINR achieves up to 2.06dB PSNR improvement over prior work, with an area of only 1914$μ$m$^2$ and a dynamic power of 6.14mW, reducing resource and power consumption by up to 97\% and improving latency by up to 93\% vs existing baselines.