SYROSYOCMay 17

A Sliced Learning Framework for Online Disturbance Identification in Quadrotor SO(3) Attitude Control

arXiv:2508.1442226.5h-index: 31
Predicted impact top 80% in SY · last 90 daysOriginality Incremental advance
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For quadrotor control practitioners, this work provides a computationally efficient and interpretable method for online disturbance identification, enabling deployment on low-cost hardware.

This paper proposes Sliced Learning, a dimension-decomposed geometric learning framework for online disturbance identification in quadrotor attitude control, achieving lightweight neural adaptation at 400 Hz on resource-constrained MCUs with real-world validation.

This paper introduces a dimension-decomposed geometric learning framework called Sliced Learning for disturbance identification in quadrotor geometric attitude control. Instead of conventional learning-from-states, this framework adopts a learning-from-error strategy by using the Lie-algebraic error representation as the input feature, enabling axis-wise space decomposition (``slicing") while preserving the SO(3) structure. This is highly consistent with the geometric mechanism of cognitive control observed in neuroscience, where neural systems organize adaptive representations within structured subspaces to enable cognitive flexibility and efficiency. Based on this framework, we develop a lightweight and structurally interpretable Sliced Adaptive-Neuro Mapping (SANM) module. The high-dimensional mapping for online identification is axially ``sliced" into multiple low-dimensional submappings (``slices"), implemented by shallow neural networks and adaptive laws. These neural networks and adaptive laws are updated online via Lyapunov-based adaptation within their respective shared subspaces. To enhance interpretability, we prove exponential convergence despite time-varying disturbances and inertia uncertainties. To our knowledge, Sliced Learning is among the first frameworks to demonstrate lightweight online neural adaptation at 400 Hz on resource-constrained microcontroller units (MCUs), such as STM32, with real-world experimental validation.

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