Scalable FPGA Framework for Real-Time Denoising in High-Throughput Imaging: A DRAM-Optimized Pipeline using High-Level Synthesis
This provides a practical solution for latency-sensitive imaging workflows in spectroscopy and microscopy, though it is incremental as it applies existing methods (FPGA, HLS) to a specific domain problem.
The paper tackled the problem of real-time denoising for high-throughput imaging workflows like PRISM, which generate data too fast for conventional processing, by presenting a scalable FPGA-based pipeline using High-Level Synthesis and DRAM optimization; the result was a kernel operating below the inter-frame interval, enabling inline denoising and reducing dataset size for downstream analysis.
High-throughput imaging workflows, such as Parallel Rapid Imaging with Spectroscopic Mapping (PRISM), generate data at rates that exceed conventional real-time processing capabilities. We present a scalable FPGA-based preprocessing pipeline for real-time denoising, implemented via High-Level Synthesis (HLS) and optimized for DRAM-backed buffering. Our architecture performs frame subtraction and averaging directly on streamed image data, minimizing latency through burst-mode AXI4 interfaces. The resulting kernel operates below the inter-frame interval, enabling inline denoising and reducing dataset size for downstream CPU/GPU analysis. Validated under PRISM-scale acquisition, this modular FPGA framework offers a practical solution for latency-sensitive imaging workflows in spectroscopy and microscopy.