Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning
This addresses a crucial bottleneck in EDA workflows by providing faster feedback without synthesis, though it appears incremental as it builds on existing graph-based and LLM approaches.
The paper tackles the problem of estimating quality metrics like area and delay for register transfer level (RTL) designs in electronic design automation by introducing StructRTL, a structure-aware graph self-supervised learning framework that uses control data flow graphs (CDFGs) and knowledge distillation from post-mapping netlists, achieving new state-of-the-art results.
Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key metrics like area and delay without the need for time-consuming logic synthesis. While recent approaches have leveraged large language models (LLMs) to derive embeddings from RTL code and achieved promising results, they overlook the structural semantics essential for accurate quality estimation. In contrast, the control data flow graph (CDFG) view exposes the design's structural characteristics more explicitly, offering richer cues for representation learning. In this work, we introduce a novel structure-aware graph self-supervised learning framework, StructRTL, for improved RTL design quality estimation. By learning structure-informed representations from CDFGs, our method significantly outperforms prior art on various quality estimation tasks. To further boost performance, we incorporate a knowledge distillation strategy that transfers low-level insights from post-mapping netlists into the CDFG predictor. Experiments show that our approach establishes new state-of-the-art results, demonstrating the effectiveness of combining structural learning with cross-stage supervision.