Hybrid unary-binary design for multiplier-less printed Machine Learning classifiers
This enables more efficient and cost-effective machine learning circuits for printed electronics applications, representing a domain-specific incremental improvement.
The paper tackles the challenge of implementing machine learning classifiers on printed electronics by proposing a hybrid unary-binary architecture that eliminates multipliers and encoders, achieving average reductions of 46% in area and 39% in power with minimal accuracy loss across six datasets.
Printed Electronics (PE) provide a flexible, cost-efficient alternative to silicon for implementing machine learning (ML) circuits, but their large feature sizes limit classifier complexity. Leveraging PE's low fabrication and NRE costs, designers can tailor hardware to specific ML models, simplifying circuit design. This work explores alternative arithmetic and proposes a hybrid unary-binary architecture that removes costly encoders and enables efficient, multiplier-less execution of MLP classifiers. We also introduce architecture-aware training to further improve area and power efficiency. Evaluation on six datasets shows average reductions of 46% in area and 39% in power, with minimal accuracy loss, surpassing other state-of-the-art MLP designs.