Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices
This work addresses the challenge of on-device training for IoT applications using RISC-V, an open architecture, but it is incremental as it adapts existing methods to a new platform.
The paper tackled the problem of enabling machine learning training on low-power RISC-V edge devices, which lack hardware support, by extending a lightweight SGD variant and introducing an 8-bit quantized version that achieved a 4x reduction in memory usage and a 2.2x speedup in training time with minimal accuracy loss.
Modern IoT devices increasingly rely on machine learning solutions to process data locally. However, the lack of graphics processing units (GPUs) or dedicated accelerators on most platforms makes on-device training largely infeasible, often requiring cloud-based services to perform this task. This procedure often raises privacy-related concerns, and creates dependency on reliable and always-on connectivity. Federated Learning (FL) is a new trend that addresses these issues by enabling decentralized and collaborative training directly on devices, but it requires highly efficient optimization algorithms. L-SGD, a lightweight variant of stochastic gradient descent, has enabled neural network training on Arm Cortex-M Microcontroller Units (MCUs). This work extends L-SGD to RISC-V-based MCUs, an open and emerging architecture that still lacks robust support for on-device training. L-SGD was evaluated on both Arm and RISC-V platforms using 32-bit floating-point arithmetic, highlighting the performance impact of the absence of Floating-Point Units (FPUs) in RISC-V MCUs. To mitigate these limitations, we introduce an 8-bit quantized version of L-SGD for RISC-V, which achieves nearly 4x reduction in memory usage and a 2.2x speedup in training time, with negligible accuracy degradation.