The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation
This addresses the need for reliable single-solution Verilog generation for hardware engineers, though it appears incremental as it builds on existing sampling techniques.
The paper tackles the problem of generating trustworthy Verilog code from requirements by proposing VCD-RNK, a discriminator model for efficient reranking that improves semantic alignment without computationally intensive test execution.
LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements and Verilog implementations, and propose VCD-RNK, a discriminator model tailored for efficient Verilog code reranking. Specifically, VCD-RNKincorporates Verilog-specific reasoning by distilling expert knowledge across three dimensions: code semantic analysis, test case generation, and functional correctness assessment. By explicitly simulating the above reasoning processes during inference, VCD-RNK effectively avoids computationally intensive test execution in existing methods.