A Parallelization Strategy for GRAND with Optimality Guarantee by Exploiting Error Pattern Tree Representation
For communication systems requiring high-throughput decoding, this work provides a parallelization strategy for GRAND that maintains optimality, addressing a key bottleneck in practical deployment.
The paper introduces a unified binary tree representation of error patterns (EP tree) for GRAND decoding, enabling parallel SGRAND with ML optimality and reduced complexity. The parallel SGRAND achieves a 3.96× latency reduction, and enhanced ORBGRAND achieves a 4.21× speedup.
Parallelism has become a central concern in modern decoding frameworks aiming to meet stringent throughput and latency requirements. Guessing Random Additive Noise Decoding (GRAND) is a recently proposed decoding paradigm that tests candidate Error Patterns (EPs) until a valid codeword is found. Among its variants, Soft GRAND (SGRAND) achieves maximum-likelihood (ML) decoding but relies on real-time generation and likelihood ordering of EPs, making parallel execution nontrivial under the ML optimality constraint. In this work, we introduce a unified binary tree representation of EPs, termed the EP tree, which formalizes the hierarchical structure underlying SGRAND and Ordered Reliability Bits (ORB) GRAND algorithms, enabling structured organization of EPs and algorithmic-level parallel exploration. Building upon this unified framework, we propose a parallel design of SGRAND that preserves ML optimality while significantly reducing decoding complexity through pruning strategies and tree-based computation. Furthermore, we develop an enhanced ORBGRAND algorithm based on the same EP tree representation, improving decoding performance toward ML while retaining parallel efficiency. Numerical experiments show that the proposed parallel SGRAND achieves a $3.96\times$ reduction in decoding latency compared with its serial counterpart, while the enhanced ORBGRAND achieves a $4.21\times$ speedup, demonstrating the effectiveness of the unified tree-based framework and its strong potential for future algorithmic and hardware optimizations.