Low Power Vision Transformer Accelerator with Hardware-Aware Pruning and Optimized Dataflow
This work addresses the problem of high power consumption in vision transformer accelerators for edge computing applications, representing an incremental improvement through algorithm-hardware co-design.
The paper tackled the computational bottleneck of Feed-Forward Networks in vision transformers by proposing a low-power accelerator with hardware-aware pruning and optimized dataflow, achieving a 61.5% reduction in operations, 59.3% reduction in weights, less than 2% accuracy loss, and energy efficiency of 2.31 TOPS/W.
Current transformer accelerators primarily focus on optimizing self-attention due to its quadratic complexity. However, this focus is less relevant for vision transformers with short token lengths, where the Feed-Forward Network (FFN) tends to be the dominant computational bottleneck. This paper presents a low power Vision Transformer accelerator, optimized through algorithm-hardware co-design. The model complexity is reduced using hardware-friendly dynamic token pruning without introducing complex mechanisms. Sparsity is further improved by replacing GELU with ReLU activations and employing dynamic FFN2 pruning, achieving a 61.5\% reduction in operations and a 59.3\% reduction in FFN2 weights, with an accuracy loss of less than 2\%. The hardware adopts a row-wise dataflow with output-oriented data access to eliminate data transposition, and supports dynamic operations with minimal area overhead. Implemented in TSMC's 28nm CMOS technology, our design occupies 496.4K gates and includes a 232KB SRAM buffer, achieving a peak throughput of 1024 GOPS at 1GHz, with an energy efficiency of 2.31 TOPS/W and an area efficiency of 858.61 GOPS/mm2.