Advancing Routing-Awareness in Analog ICs Floorplanning
This work addresses a prevalent concern among layout engineers for routing-aware floorplanning solutions in analog IC design, representing a strong specific gain in this domain.
The paper tackled the problem of routing-aware floorplanning for analog integrated circuits by developing an automatic engine using reinforcement learning and relational graph convolutional neural networks, achieving a 13.8% reduction in dead space, a 40.6% reduction in wirelength, and a 73.4% increase in routing success compared to past learning-based state-of-the-art techniques.
The adoption of machine learning-based techniques for analog integrated circuit layout, unlike its digital counterpart, has been limited by the stringent requirements imposed by electric and problem-specific constraints, along with the interdependence of floorplanning and routing steps. In this work, we address a prevalent concern among layout engineers regarding the need for readily available routing-aware floorplanning solutions. To this extent, we develop an automatic floorplanning engine based on reinforcement learning and relational graph convolutional neural network specifically tailored to condition the floorplan generation towards more routable outcomes. A combination of increased grid resolution and precise pin information integration, along with a dynamic routing resource estimation technique, allows balancing routing and area efficiency, eventually meeting industrial standards. When analyzing the place and route effectiveness in a simulated environment, the proposed approach achieves a 13.8% reduction in dead space, a 40.6% reduction in wirelength and a 73.4% increase in routing success when compared to past learning-based state-of-the-art techniques.