Accelerating Electrostatics-based Global Placement with Enhanced FFT Computation
For VLSI placement practitioners, this provides a faster method for electrostatics-based placement without sacrificing quality.
This work accelerates electrostatics-based global placement by using an enhanced FFT technique (AccFFT), achieving a 5.78x speedup in FFT computation and 32% total runtime improvement over ePlace-MS with a 1.0% wirelength reduction.
Global placement is essential for high-quality and efficient circuit placement for complex modern VLSI designs. Recent advancements, such as electrostatics-based analytic placement, have improved scalability and solution quality. This work demonstrates that using an accelerated FFT technique, AccFFT, for electric field computation significantly reduces runtime. Experimental results on standard benchmarks show significant improvements when incorporated into the ePlace-MS and Pplace-MS algorithms, e.g., a 5.78x speedup in FFT computation and a 32% total runtime improvement against ePlace-MS, with 1.0% reduction of scaled half-perimeter wirelength after detailed placement.