FPGA-based Lane Detection System incorporating Temperature and Light Control Units
This work addresses lane detection for intelligent vehicles in varying conditions, but it is incremental as it applies an existing method (Sobel algorithm) with hardware optimizations and added control units.
The paper tackles lane detection for intelligent vehicles by proposing an FPGA-based system using the Sobel algorithm, achieving a processing time of 1.17 ms per 416 x 416 image at 150 MHz and outputting lane details with integrated environmental control units.
Intelligent vehicles are one of the most important outcomes gained from the world tendency toward automation. Applications of IVs, whether in urban roads or robot tracks, do prioritize lane path detection. This paper proposes an FPGA-based Lane Detector Vehicle LDV architecture that relies on the Sobel algorithm for edge detection. Operating on 416 x 416 images and 150 MHz, the system can generate a valid output every 1.17 ms. The valid output consists of the number of present lanes, the current lane index, as well as its right and left boundaries. Additionally, the automated light and temperature control units in the proposed system enhance its adaptability to the surrounding environmental conditions.