FeNN-DMA: A RISC-V SoC for SNN acceleration
This addresses energy-efficient SNN acceleration for spatio-temporal tasks like keyword spotting and video classification, though it is incremental as it builds on existing FPGA and RISC-V technologies.
The authors tackled the inefficiency of simulating Spiking Neural Networks (SNNs) on standard accelerators by developing FeNN-DMA, a RISC-V-based system-on-chip for FPGAs, achieving state-of-the-art classification accuracy on Spiking Heidelberg Digits and Neuromorphic MNIST tasks.
Spiking Neural Networks (SNNs) are a promising, energy-efficient alternative to standard Artificial Neural Networks (ANNs) and are particularly well-suited to spatio-temporal tasks such as keyword spotting and video classification. However, SNNs have a much lower arithmetic intensity than ANNs and are therefore not well-matched to standard accelerators like GPUs and TPUs. Field Programmable Gate Arrays(FPGAs) are designed for such memory-bound workloads and here we develop a novel, fully-programmable RISC-V-based system-on-chip (FeNN-DMA), tailored to simulating SNNs on modern UltraScale+ FPGAs. We show that FeNN-DMA has comparable resource usage and energy requirements to state-of-the-art fixed-function SNN accelerators, yet it is capable of simulating much larger and more complex models. Using this functionality, we demonstrate state-of-the-art classification accuracy on the Spiking Heidelberg Digits and Neuromorphic MNIST tasks.