Event-Driven Digital-Time-Domain Inference Architectures for Tsetlin Machines
This addresses inference efficiency problems for edge computing applications, but it is incremental as it builds on existing Tsetlin machine architectures.
The paper tackles the high latency and power consumption of Tsetlin machine inference by proposing a digital-time-domain computing approach, achieving orders-of-magnitude improvements in energy efficiency and throughput compared to a baseline.
Machine learning fits model parameters to approximate input-output mappings, predicting unknown samples. However, these models often require extensive arithmetic computations during inference, increasing latency and power consumption. This paper proposes a digital-time-domain computing approach for Tsetlin machine (TM) inference process to address these challenges. This approach leverages a delay accumulation mechanism to mitigate the costly arithmetic sums of classes and employs a Winner-Takes-All scheme to replace conventional magnitude comparators. Specifically, a Hamming distance-driven time-domain scheme is implemented for multi-class TMs. Furthermore, differential delay paths, combined with a leading-ones-detector logarithmic delay compression digital-time-domain scheme, are utilised for the coalesced TMs, accommodating both binary-signed and exponential-scale delay accumulation issues. Compared to the functionally equivalent, post-implementation digital TM architecture baseline, the proposed architecture demonstrates orders-of-magnitude improvements in energy efficiency and throughput.