LILogic Net: Compact Logic Gate Networks with Learnable Connectivity for Efficient Hardware Deployment
This enables efficient deployment on low-power digital hardware, though it is incremental by extending gradient-based methods to optimize connections.
The paper tackles the problem of designing energy-efficient machine learning models for hardware deployment by optimizing both logic gates and their interconnections, achieving 98.45% test accuracy on MNIST with only 8,000 gates and 60.98% on CIFAR-10 with 256,000 gates.
Efficient deployment of machine learning models ultimately requires taking hardware constraints into account. The binary logic gate is the fundamental building block of all digital chips. Designing models that operate directly on these units enables energy-efficient computation. Recent work has demonstrated the feasibility of training randomly connected networks of binary logic gates (such as OR and NAND) using gradient-based methods. We extend this approach by using gradient descent not only to select the logic gates but also to optimize their interconnections (the connectome). Optimizing the connections allows us to substantially reduce the number of logic gates required to fit a particular dataset. Our implementation is efficient both at training and inference: for instance, our LILogicNet model with only 8,000 gates can be trained on MNIST in under 5 minutes and achieves 98.45% test accuracy, matching the performance of state-of-the-art models that require at least two orders of magnitude more gates. Moreover, for our largest architecture with 256,000 gates, LILogicNet achieves 60.98% test accuracy on CIFAR-10 exceeding the performance of prior logic-gate-based models with a comparable gate budget. At inference time, the fully binarized model operates with minimal compute overhead, making it exceptionally efficient and well suited for deployment on low-power digital hardware.