hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware
This provides a flexible tool for developers and researchers in fields like commercial and scientific computing where efficient ML inference is critical, though it is incremental as it builds on existing HLS compilers and frameworks.
The authors tackled the problem of accelerating deep learning inference on reconfigurable hardware by developing hls4ml, an open-source platform that translates ML models into high-level synthesis code for FPGAs or ASICs, enabling low latency, resource efficiency, and power savings in various applications.
We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.