David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
This addresses the sustainability and expense of domain-specific AI tasks for hardware designers, though it appears incremental by applying existing agentic methods to a new domain.
The paper tackles the problem of high computational and energy costs of large language models in hardware design by testing small language models with an agentic AI framework on NVIDIA's Verilog benchmark, achieving near-LLM performance at a fraction of the cost.
Large Language Model(LLM) inference demands massive compute and energy, making domain-specific tasks expensive and unsustainable. As foundation models keep scaling, we ask: Is bigger always better for hardware design? Our work tests this by evaluating Small Language Models coupled with a curated agentic AI framework on NVIDIA's Comprehensive Verilog Design Problems(CVDP) benchmark. Results show that agentic workflows: through task decomposition, iterative feedback, and correction - not only unlock near-LLM performance at a fraction of the cost but also create learning opportunities for agents, paving the way for efficient, adaptive solutions in complex design tasks.