When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation
This addresses reliability issues in LLM-assisted hardware design, offering a domain-specific incremental improvement.
The paper tackles the problem of unreliable hardware code generation by LLMs due to memorization of proprietary IP and unsafe patterns, proposing an unlearning framework that achieves effective removal of problematic knowledge while preserving code generation capabilities, supporting forget sets up to 3x larger with a single training epoch.
Large Language Models (LLMs) have shown strong potential in accelerating digital hardware design through automated code generation. Yet, ensuring their reliability remains a critical challenge, as existing LLMs trained on massive heterogeneous datasets often exhibit problematic memorization of proprietary intellectual property (IP), contaminated benchmarks, and unsafe coding patterns. To mitigate these risks, we propose a novel unlearning framework tailored for LLM-based hardware code generation. Our method combines (i) a syntax-preserving unlearning strategy that safeguards the structural integrity of hardware code during forgetting, and (ii) a fine-grained floor-aware selective loss that enables precise and efficient removal of problematic knowledge. This integration achieves effective unlearning without degrading LLM code generation capabilities. Extensive experiments show that our framework supports forget sets up to 3x larger, typically requiring only a single training epoch, while preserving both syntactic correctness and functional integrity of register-transfer level (RTL) codes. Our work paves an avenue towards reliable LLM-assisted hardware design.