DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
This work addresses a domain-specific problem for FPGA accelerator designers by providing a novel method to improve optimization, though it is incremental as it builds on existing HLS tools.
The paper tackled the problem of fixed optimization strategies in High-Level Synthesis (HLS) tools for FPGA accelerators, which limit effectiveness, by proposing DAPO, a framework that uses graph contrastive and reinforcement learning to tailor strategies, resulting in a 2.36x speedup over Vitis HLS on average.
High-Level Synthesis (HLS) tools are widely adopted in FPGA-based domain-specific accelerator design. However, existing tools rely on fixed optimization strategies inherited from software compilations, limiting their effectiveness. Tailoring optimization strategies to specific designs requires deep semantic understanding, accurate hardware metric estimation, and advanced search algorithms -- capabilities that current approaches lack. We propose DAPO, a design structure-aware pass ordering framework that extracts program semantics from control and data flow graphs, employs contrastive learning to generate rich embeddings, and leverages an analytical model for accurate hardware metric estimation. These components jointly guide a reinforcement learning agent to discover design-specific optimization strategies. Evaluations on classic HLS designs demonstrate that our end-to-end flow delivers a 2.36 speedup over Vitis HLS on average.