GIC-DLC: Differentiable Logic Circuits for Hardware-Friendly Grayscale Image Compression
This addresses the problem of deploying learned compression on edge devices like smartphones and drones, though it appears incremental as it builds on existing neural codec approaches with hardware optimization.
The paper tackles the problem of neural image codecs having high computational overhead for energy-constrained devices by proposing GIC-DLC, a hardware-aware codec using differentiable logic circuits. Results show it outperforms traditional codecs in compression efficiency while reducing energy consumption and latency.
Neural image codecs achieve higher compression ratios than traditional hand-crafted methods such as PNG or JPEG-XL, but often incur substantial computational overhead, limiting their deployment on energy-constrained devices such as smartphones, cameras, and drones. We propose Grayscale Image Compression with Differentiable Logic Circuits (GIC-DLC), a hardware-aware codec where we train lookup tables to combine the flexibility of neural networks with the efficiency of Boolean operations. Experiments on grayscale benchmark datasets show that GIC-DLC outperforms traditional codecs in compression efficiency while allowing substantial reductions in energy consumption and latency. These results demonstrate that learned compression can be hardware-friendly, offering a promising direction for low-power image compression on edge devices.