SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence
This addresses the challenge of component recognition and connectivity inference in circuit design automation, providing a significant improvement over existing methods.
The paper tackled the problem of converting circuit schematic images into machine-readable netlists by developing SINA, an automated generator that achieved 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.
Current methods for converting circuit schematic images into machine-readable netlists struggle with component recognition and connectivity inference. In this paper, we present SINA, an open-source, fully automated circuit schematic image-to-netlist generator. SINA integrates deep learning for accurate component detection, Connected-Component Labeling (CCL) for precise connectivity extraction, and Optical Character Recognition (OCR) for component reference designator retrieval, while employing a Vision-Language Model (VLM) for reliable reference designator assignments. In our experiments, SINA achieves 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.