A Parameterizable Convolution Accelerator for Embedded Deep Learning Applications
This work addresses optimization across multiple constraints like latency and power for embedded systems, but it is incremental as it builds on existing FPGA accelerator methods.
The paper tackles the challenge of designing convolutional neural network accelerators for embedded deep learning applications by proposing a hardware-software co-design methodology using high-level synthesis tools for parameterization, resulting in improved performance over non-parameterized approaches.
Convolutional neural network (CNN) accelerators implemented on Field-Programmable Gate Arrays (FPGAs) are typically designed with a primary focus on maximizing performance, often measured in giga-operations per second (GOPS). However, real-life embedded deep learning (DL) applications impose multiple constraints related to latency, power consumption, area, and cost. This work presents a hardware-software (HW/SW) co-design methodology in which a CNN accelerator is described using high-level synthesis (HLS) tools that ease the parameterization of the design, facilitating more effective optimizations across multiple design constraints. Our experimental results demonstrate that the proposed design methodology is able to outperform non-parameterized design approaches, and it can be easily extended to other types of DL applications.