Physical Analogue Kolmogorov-Arnold Networks based on Reconfigurable Nonlinear-Processing Units
For hardware neural network designers, this provides a realistic silicon-based path to energy- and area-efficient edge inference, though it is an incremental hardware implementation of an existing KAN architecture.
The paper introduces a physical analogue Kolmogorov-Arnold Network (aKAN) using reconfigurable nonlinear-processing units (RNPUs) on silicon, demonstrating function approximation with fewer parameters than MLPs and achieving ~250 pJ per inference and ~600 ns latency, offering 100-1000x energy reduction and 10x area reduction over digital fixed-point MLPs.
Kolmogorov-Arnold Networks (KANs) shift neural computation from linear layers to learnable nonlinear edge functions, but implementing these nonlinearities efficiently in hardware remains an open challenge. Here we introduce a physical analogue KAN architecture in which edge functions are realized in materia using reconfigurable nonlinear-processing units (RNPUs): multi-terminal nanoscale silicon devices whose input-output characteristics are tuned via control voltages. By combining multiple RNPUs into an edge processor and assembling these blocks into a reconfigurable analogue KAN (aKAN) architecture with integrated mixed-signal interfacing, we establish a realistic system-level hardware implementation that enables compact KAN-style regression and classification with programmable nonlinear transformations. Using experimentally calibrated RNPU models and hardware measurements, we demonstrate accurate function approximation across increasing task complexity while requiring fewer or comparable trainable parameters than multilayer perceptrons (MLPs). System-level estimates indicate an energy per inference of $\sim$250 pJ and an end-to-end inference latency of $\sim$600 ns for a representative workload, corresponding to a $\sim$10$^{2}$-10$^{3}\times$ reduction in energy accompanied by a $\sim$10$\times$ reduction in area compared to a digital fixed-point MLP at similar approximation error. These results establish RNPUs as scalable, hardware-native nonlinear computing primitives and identify analogue KAN architectures as a realistic silicon-based pathway toward energy-, latency-, and footprint-efficient analogue neural-network hardware, particularly for edge inference.