ETARMar 18

Probabilistic approximate optimization using single-photon avalanche diode arrays

arXiv:2602.1394312.6h-index: 32
Predicted impact top 24% in ET · last 90 daysOriginality Incremental advance
AI Analysis

This addresses the challenge of building practical probabilistic computers using nanoscale CMOS devices by accommodating their non-idealities, though it is incremental as it builds on the existing PAOA framework.

The paper tackled combinatorial optimization problems by implementing the Probabilistic Approximate Optimization Algorithm (PAOA) on a 64×64 single-photon avalanche diode array, achieving high approximation ratios on 26-spin Sherrington-Kirkpatrick instances with up to 17 layers.

Combinatorial optimization problems are central to science and engineering and specialized hardware from quantum annealers to classical Ising machines are being actively developed to address them. These systems typically sample from a fixed energy landscape defined by the problem Hamiltonian encoding the discrete optimization problem. The recently introduced Probabilistic Approximate Optimization Algorithm (PAOA) takes a different approach: it treats the optimization landscape itself as variational, iteratively learning circuit parameters from samples. Here, we demonstrate PAOA on a 64$\times$64 perimeter-gated single-photon avalanche diode (pgSPAD) array fabricated in 0.35 $μ$m CMOS, the first realization of the algorithm using intrinsically stochastic nanodevices. Each p-bit exhibits a device-specific, asymmetric (Gompertz-type) activation function due to dark-count variability. Rather than calibrating devices to enforce a uniform symmetric (logistic/tanh) activation, PAOA learns around device variations, absorbing residual activation and other mismatches into the variational parameters. On canonical 26-spin Sherrington-Kirkpatrick instances, PAOA achieves high approximation ratios with $2p$ parameters ($p$ up to 17 layers), and pgSPAD-based inference closely tracks CPU simulations. These results show that variational learning can accommodate the non-idealities inherent to nanoscale devices, suggesting a practical path toward larger-scale, CMOS-compatible probabilistic computers.

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