Hexagon-MLIR: An AI Compilation Stack For Qualcomm's Neural Processing Units (NPUs)
This provides developers with a more flexible, open-source tool for AI compilation on Qualcomm NPUs, though it is incremental as it builds on existing MLIR frameworks and complements commercial toolchains.
The paper tackles the problem of compiling AI workloads for Qualcomm Hexagon NPUs by presenting Hexagon-MLIR, an open-source compilation stack that accelerates deployment of Triton kernels and PyTorch models, generating mega-kernels to improve data locality and reduce bandwidth bottlenecks.
In this paper, we present Hexagon-MLIR,an open-source compilation stack that targets Qualcomm Hexagon Neural Processing Unit (NPU) and provides unified support for lowering Triton kernels and PyTorch models . Built using the MLIR framework, our compiler applies a structured sequence of passes to exploit NPU architectural features to accelerate AI workloads. It enables faster deployment of new Triton kernels (hand-written or subgraphs from PyTorch 2.0), for our target by providing automated compilation from kernel to binary. By ingesting Triton kernels, we generate mega-kernels that maximize data locality in the NPU's Tightly Coupled Memory (TCM), reducing the bandwidth bottlenecks inherent in library-based approaches. This initiative complements our commercial toolchains by providing developers with an open-source MLIR-based compilation stack that gives them a path to advance AI compilation capabilities through a more flexible approach. Hexagon-MLIR is a work-in-progress, and we are continuing to add many more optimizations and capabilities in this effort.