Agentic AI-based Coverage Closure for Formal Verification
This addresses the challenge of coverage closure in integrated chip verification, which is critical for sign-off but often fails within project timelines, though it appears incremental as it builds on existing AI/LLM techniques.
The paper tackles the problem of achieving full coverage in formal verification for chip development by introducing an agentic AI-driven workflow that uses LLM-enabled Generative AI to automate coverage analysis and generate formal properties, resulting in measurable increases in coverage metrics correlated with design complexity.
Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to achieve full coverage within project timelines. This study presents an agentic AI-driven workflow that utilizes Large Language Model (LLM)-enabled Generative AI (GenAI) to automate coverage analysis for formal verification, identify coverage gaps, and generate the required formal properties. The framework accelerates verification efficiency by systematically addressing coverage holes. Benchmarking open-source and internal designs reveals a measurable increase in coverage metrics, with improvements correlated to the complexity of the design. Comparative analysis validates the effectiveness of this approach. These results highlight the potential of agentic AI-based techniques to improve formal verification productivity and support comprehensive coverage closure.