Efficient Time-Aware Partitioning of Quantum Circuits for Distributed Quantum Computing
For quantum computing researchers and compiler designers, this work provides an efficient compilation tool to minimize communication overhead in near-term distributed quantum hardware.
The paper tackles the high communication overhead in distributed quantum computing by proposing a beam-search-based heuristic for partitioning quantum circuits. The algorithm achieves lower communication costs than static baselines across varying circuit sizes, depths, and network topologies, with quadratic time and space complexity in qubit count and linear in circuit depth.
To overcome the physical limitations of scaling monolithic quantum computers, distributed quantum computing (DQC) interconnects multiple smaller-scale quantum processing units (QPUs) to form a quantum network. However, this approach introduces a critical challenge, namely the high cost of quantum communication between remote QPUs incurred by quantum state teleportation and quantum gate teleportation. To minimize this communication overhead, DQC compilers must strategically partition quantum circuits by mapping logical qubits to distributed physical QPUs. Static graph partitioning methods are fundamentally ill-equipped for this task as they ignore execution dynamics and underlying network topology, while metaheuristics require substantial computational runtime. In this work, we propose a heuristic based on beam search to solve the circuit partitioning problem. Our time-aware algorithm incrementally constructs a low-cost sequence of qubit assignments across successive time steps to minimize overall communication overhead. The time and space complexities of the proposed algorithm scale quadratically with the number of qubits and linearly with circuit depth, offering a significant computational speedup over common metaheuristics. We demonstrate that our proposed algorithm consistently achieves significantly lower communication costs than static baselines across varying circuit sizes, depths, and network topologies, providing an efficient compilation tool for near-term distributed quantum hardware.