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Geometry-Aware Probabilistic Circuits via Voronoi Tessellations

arXiv:2603.11946v112.2h-index: 13
Predicted impact top 71% in LG · last 90 daysOriginality Incremental advance
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This work addresses a bottleneck in probabilistic circuits for researchers in machine learning, offering incremental improvements by integrating geometric structure while maintaining tractability.

The paper tackles the problem of probabilistic circuits (PCs) having data-independent mixture weights that limit their ability to capture local data geometry, and proposes using Voronoi tessellations to incorporate geometric structure, with results including an approximate inference framework with bounds and a structural condition for exact tractability, validated empirically on density estimation tasks.

Probabilistic circuits (PCs) enable exact and tractable inference but employ data independent mixture weights that limit their ability to capture local geometry of the data manifold. We propose Voronoi tessellations (VT) as a natural way to incorporate geometric structure directly into the sum nodes of a PC. However, naïvely introducing such structure breaks tractability. We formalize this incompatibility and develop two complementary solutions: (1) an approximate inference framework that provides guaranteed lower and upper bounds for inference, and (2) a structural condition for VT under which exact tractable inference is recovered. Finally, we introduce a differentiable relaxation for VT that enables gradient-based learning and empirically validate the resulting approach on standard density estimation tasks.

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