An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration
This work addresses layout generation challenges for semiconductor design-technology co-optimization, offering incremental improvements in efficiency and quality for domain-specific applications.
The paper tackled the problem of generating standard-cell layouts for advanced semiconductor nodes with arbitrary gear ratios and offsets, resulting in CPCell, a framework that improves layout quality and scales to netlists with up to 48 transistors through co-optimization techniques.
Advanced nodes decouple contacted poly pitch (CPP) and lower-metal pitch to improve routability. We present CPCell, an efficient standard-cell layout generation framework, to support arbitrary gear ratio (GR) and offset parameters through a fine-grained layered grid graph and constraint-programming-based placement-routing co-optimization. Layout quality is improved via Middle-of-Line routing, M0 pin enablement, pin accessibility constraints and a weighted multi-objective formulation that jointly optimizes cell layouts. To scale to netlists with up to 48 transistors, we incorporate acceleration techniques including transistor clustering, identical transistor partitioning, routing lower bound tightening and early termination strategies. Comprehensive cell-level and block-level studies are conducted to evaluate GR and offset choices, quantify the benefits of the proposed objectives and assess their impact on power, performance, area and IR-drop outcomes.