ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM
This provides a portable solution for real-time systems developers to mitigate memory interference, though it is incremental as it builds on existing ETM hardware.
The authors tackled memory interference in real-time multicore systems by repurposing the Embedded Trace Macrocell (ETM) into a hardware-assisted memory bandwidth regulator, demonstrating effectiveness on 64-bit Arm boards and unlocking new regulation options compared to prior methods.
The Embedded Trace Macrocell (ETM) is a standard component of Arm's CoreSight architecture, present in a wide range of platforms and primarily designed for tracing and debugging. In this work, we demonstrate that it can be repurposed to implement a novel hardware-assisted memory bandwidth regulator, providing a portable and effective solution to mitigate memory interference in real-time multicore systems. ETM2 requires minimal software intervention and bridges the gap between the fine-grained microsecond resolution of MemPol and the portability and reaction time of interrupt-based solutions, such as MemGuard. We assess the effectiveness and portability of our design with an evaluation on a large number of 64-bit Arm boards, and we compare ETM2 with previous works using a setup based on the San Diego Vision Benchmark Suite on the AMD Zynq UltraScale+. Our results show the scalability of the approach and highlight the design trade-offs it enables. ETM2 is effective in enforcing per-core memory bandwidth regulation and unlocks new regulation options that were infeasible under MemGuard and MemPol.