SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization
This work addresses the problem of improving RTL synthesis and summarization for hardware designers by incorporating symbolic planning, though it appears incremental as it builds on existing prompting and RAG methods.
The paper tackles the challenge of Register-Transfer Level (RTL) synthesis and summarization for hardware design automation by introducing SYMDIREC, a neuro-symbolic framework that decomposes tasks into symbolic subgoals and uses retrieval and LLM reasoning to assemble verified outputs, achieving ~20% higher Pass@1 rates for synthesis and 15-20% ROUGE-L improvements for summarization over baselines.
Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax, limited supervision, and weak alignment with natural language. Existing prompting and retrieval-augmented generation (RAG) methods have not incorporated symbolic planning, limiting their structural precision. We introduce SYMDIREC, a neuro-symbolic framework that decomposes RTL tasks into symbolic subgoals, retrieves relevant code via a fine-tuned retriever, and assembles verified outputs through LLM reasoning. Supporting both Verilog and VHDL without LLM fine-tuning, SYMDIREC achieves ~20% higher Pass@1 rates for synthesis and 15-20% ROUGE-L improvements for summarization over prompting and RAG baselines, demonstrating the benefits of symbolic guidance in RTL tasks.