ARDCMar 24

Characterizing CPU-Induced Slowdowns in Multi-GPU LLM Inference

arXiv:2603.2277464.3h-index: 3
AI Analysis

This addresses performance bottlenecks for users deploying multi-GPU LLM inference systems, though it is incremental as it focuses on optimizing existing configurations rather than introducing new methods.

The paper tackles the problem of CPU-induced slowdowns limiting multi-GPU performance in large language model inference, showing that increasing CPU cores reduces time-to-first-token latency by 1.36-5.40x without needing extra GPUs.

Large-scale machine learning workloads increasingly rely on multi-GPU systems, yet their performance is often limited by an overlooked component: the CPU. Through a detailed study of modern large language model (LLM) inference and serving workloads, we find that multi-GPU performance frequently degrades not because GPUs are saturated, but because CPUs fail to keep the GPUs busy. Under limited CPU allocations, systems exhibit symptoms such as delayed kernel launch, stalled communication, and increased tokenization latency, leading to severe GPU underutilization even when ample GPU resources are available. This work presents a systematic analysis of CPU-induced slowdowns in multi-GPU LLM inference. We show that these bottlenecks persist even in serving stacks that employ process-level separation and modern GPU-side optimizations such as CUDA Graphs. Since the marginal cost of additional CPU cores is small relative to GPU instance pricing, our evaluation indicates that increasing the number of CPU cores can substantially improve performance and stability at minimal additional cost. Under moderate serving load, we observe that CPU-starved configurations frequently time out, while providing adequate CPU resources restores responsiveness and reduces time-to-first-token (TTFT) latency by 1.36-5.40x across configurations, all without requiring additional GPUs. This work shows that CPU provisioning is a crucial factor in multi-GPU LLM inference configuration, helping prevent control-side bottlenecks.

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