PIM-CACHE: High-Efficiency Content-Aware Copy for Processing-In-Memory
This work addresses performance inefficiencies in PIM systems for applications like genomics, though it appears incremental as it builds on existing hardware solutions like UPMEM's technology.
The paper tackles the bottleneck of coarse-grained data transfers in processing-in-memory (PIM) architectures by introducing PIM-CACHE, a lightweight data staging layer that dynamically eliminates redundant transfers through content-aware copy, achieving reduced transfer overhead as demonstrated on synthetic workloads and real-world genome datasets.
Processing-in-memory (PIM) architectures bring computation closer to data, reducing the processor-memory transfer bottleneck in traditional processor-centric designs. Novel hardware solutions, such as UPMEM's in-memory processing technology, achieve this by integrating low-power DRAM processing units (DPUs) into memory DIMMs, enabling massive parallelism and improved memory bandwidth. However, paradoxically, these PIM architectures introduce mandatory coarse-grained data transfers between host DRAM and DPUs, which often become the new bottleneck. We present PIM-CACHE, a lightweight data staging layer that dynamically eliminates redundant data transfers to PIM DPUs by exploiting workload similarity, achieving content-aware copy (CAC). We evaluate PIM-CACHE on both synthetic workloads and real-world genome datasets, demonstrating its effectiveness in reducing PIM data transfer overhead.