Generalizable Verilog Modeling Framework for Synchronous and Asynchronous Superconducting Pulse-Based Logic Gates
This work addresses a domain-specific problem for researchers and engineers in superconducting computing by providing a scalable modeling tool, though it is incremental as it builds on prior efforts with limited coverage.
The paper tackles the challenge of modeling superconducting Single Flux Quantum (SFQ) logic gates, which are pulse-based and incompatible with conventional hardware description languages, by presenting a Verilog-based framework that supports both synchronous and asynchronous gates and maintains SDF compatibility, validated through device-level simulations and RTL simulations of mixed circuits.
Superconducting Single Flux Quantum (SFQ) logic offers a promising platform for ultra-low-power, high-frequency computing. However, their pulse-based nature poses challenges for scalable modeling, design, and verification using conventional hardware description languages (HDLs), which are designed for level-based digital logic. Prior efforts have required complex Verilog support modules to enable Standard Delay Format (SDF) compatibility and have provided limited coverage of SFQ cell types. This work presents a Verilog-based modeling framework for SFQ gates that enables functional and timing verification while maintaining compatibility with Standard Delay Format (SDF) back annotation and is the first framework to support both synchronous and asynchronous SFQ gates. The proposed models are validated through device-level simulations, demonstrating correct functionality and timing constraint coverage. RTL simulation of mixed synchronous-asynchronous circuits further demonstrate the utility of the proposed framework.