Per-Bank Memory Bandwidth Regulation for Predictable and Performant Real-Time System
This addresses the need for predictable and efficient real-time systems by mitigating adversarial bank contention in shared DRAM, representing a domain-specific incremental improvement over prior per-core regulation methods.
The paper tackles the problem of DRAM bank-level interference degrading performance and real-time guarantees in multicore SoCs by designing a per-bank memory bandwidth regulator, achieving a 5.74x average throughput improvement for best-effort workloads over traditional approaches while maintaining performance isolation for real-time workloads.
Modern multicore system-on-chips (SoCs) share off-chip DRAM across cores, where bank-level interference can significantly degrade performance and threaten real-time guarantees. While prior work has focused on per-core bandwidth regulation, these approaches treat main memory as a monolithic resource and overlook DRAM's inherent bank-level parallelism. We show that DRAM interference is fundamentally a bank-level phenomenon. We characterize the guaranteed bandwidth of modern DRAM, demonstrate that it remains effectively constant across generations, and show how this limitation can be exploited by single-bank attacks. These results highlight the need for bank-aware memory management for predictable and efficient real-time systems. We design and implement a novel per-bank memory bandwidth regulator in an open-source RISC-V SoC and evaluate it using FireSim with both synthetic and real-world workloads. Our evaluation demonstrates that per-bank regulation effectively mitigates adversarial bank contention and achieves a 5.74x average throughput improvement for best-effort workloads over traditional bank-oblivious approaches while providing the same-level of performance isolation guarantees for real-time workloads.