HPCCFA: Leveraging Hardware Performance Counters for Control Flow Attestation
This work addresses runtime security for remote systems using TEEs, offering a hardware-backed solution for control flow attestation on commodity CPUs, though it appears incremental as an extension of existing TEE mechanisms.
The paper tackled the problem of runtime attacks in Trusted Execution Environments (TEEs) by introducing HPCCFA, a method using Hardware Performance Counters (HPCs) for Control Flow Attestation (CFA) to detect control flow violations, demonstrating feasibility on a Keystone implementation for RISC-V with a trade-off between detection reliability and performance overhead.
Trusted Execution Environments (TEEs) allow the secure execution of code on remote systems without the need to trust their operators. They use static attestation as a central mechanism for establishing trust, allowing remote parties to verify that their code is executed unmodified in an isolated environment. However, this form of attestation does not cover runtime attacks, where an attacker exploits vulnerabilities in the software inside the TEE. Control Flow Attestation (CFA), a form of runtime attestation, is designed to detect such attacks. In this work, we present a method to extend TEEs with CFA and discuss how it can prevent exploitation in the event of detected control flow violations. Furthermore, we introduce HPCCFA, a mechanism that uses HPCs for CFA purposes, enabling hardware-backed trace generation on commodity CPUs. We demonstrate the feasibility of HPCCFA on a proof-of-concept implementation for Keystone on RISC-V. Our evaluation investigates the interplay of the number of measurement points and runtime protection, and reveals a trade-off between detection reliability and performance overhead.