RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
This work addresses communication bottlenecks in multi-FPGA systems for VLSI emulation and rapid prototyping, offering a significant improvement over existing methods.
The paper tackled the problem of inefficient hypergraph partitioning for multi-FPGA systems by developing RePart, a framework that integrates logic replication with topology-aware optimization, resulting in a 52.3% reduction in total hop distance and an 11.1x speedup over state-of-the-art methods.
Multi-FPGA systems (MFS) are widely adopted for VLSI emulation and rapid prototyping. In an MFS, FPGAs connect only to a limited number of neighbors through bandwidth-constrained links, so inter-FPGA communication cost depends on network topology. This setting exposes two fundamental limitations of existing MFS-aware partitioning methods: conventional hypergraph partitioners focus solely on cut size and ignore topological structure, and they leave substantial FPGA resources unused due to conservative balance margins. We present RePart, a fully customized multilevel hypergraph partitioning framework for MFS that integrates logic replication with topology-aware optimization. RePart introduces three coordinated innovations across the multilevel pipeline: FPGA-aware dynamic coarsening, heat-value guided assignment, and replication-deletion supported refinement. Extensive experiments on the Titan23 and EDA Elite Challenge Contest benchmarks show that RePart reduces total hop distance by 52.3% on average over state-of-the-art hypergraph partitioners with an 11.1x speedup, and outperforms the EDA Elite Challenge winners. Code is available at: https://github.com/Welement-zyf/RePart.