Assertain: Automated Security Assertion Generation Using Large Language Models
This addresses hardware security verification for system-on-chip designers by automating a manual bottleneck, though it appears incremental as an enhancement of existing LLM methods.
The paper tackles the bottleneck of manual security property specification in hardware verification by developing Assertain, an automated framework that generates security assertions using large language models. Results show it outperforms GPT-5 by 61.22% in correct assertion generation and up to 67.92% in architectural flaw detection on 11 hardware designs.
The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property verification. This paper presents Assertain, an automated framework that integrates RTL design analysis, Common Weakness Enumeration (CWE) mapping, and threat model intelligence to automatically generate security properties and executable SystemVerilog Assertions. Assertain leverages large language models with a self-reflection refinement mechanism to ensure both syntactic correctness and semantic consistency. Evaluated on 11 representative hardware designs, Assertain outperforms GPT-5 by 61.22%, 59.49%, and 67.92% in correct assertion generation, unique CWE coverage, and architectural flaw detection, respectively. These results demonstrate that Assertain significantly expands vulnerability coverage, improves assertion quality, and reduces manual effort in hardware security verification.