DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration
This addresses the problem of high power and area consumption in low-precision arithmetic for AI and edge computing, representing an incremental improvement in hardware design.
The paper tackled the need for energy-efficient floating-point MAC units in AI acceleration by proposing a dual-precision processing engine supporting FP8 and FP4 formats, achieving up to 60.4% area reduction and 86.6% power savings compared to state-of-the-art designs.
The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a fully pipelined dual-precision floating-point MAC processing engine supporting FP8 formats (E4M3, E5M2) and FP4 formats (E2M1, E1M2), specifically optimized for low-power and high-throughput AI workloads. The proposed architecture employs a novel bit-partitioning technique that enables a single 4-bit unit multiplier to operate either as a standard 4x4 multiplier for FP8 or as two parallel 2x2 multipliers for 2-bit operands, achieving 100 percent hardware utilization without duplicating logic. Implemented in 28 nm technology, the proposed processing engine achieves an operating frequency of 1.94 GHz with an area of 0.00396 mm^2 and power consumption of 2.13 mW, resulting in up to 60.4 percent area reduction and 86.6 percent power savings compared to state-of-the-art designs.