Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit - A P-Bit
This work addresses the need for novel computing schemes to overcome semiconductor scaling limits and enhance neuromorphic computing, offering a potential solution for low-power probabilistic computing integrated with existing CMOS technology.
The researchers tackled the challenge of creating a power-efficient probabilistic computing building block by experimentally demonstrating the first fully CMOS-integrated stochastic magnetic tunnel junction-based probabilistic bit, which generates rail-to-rail stochastic output using only 3 transistors and 1 sMTJ and was validated in simulations for probabilistic logic circuits.
Ongoing semiconductor scaling challenges and the rise of neuromorphic computing have sparked interest in exploring novel computing schemes to achieve higher power efficiency and computational capabilities. Probabilistic computing is one candidate that endows low power consumption, capability of solving probability-encoded computational problems, and the ease of integration with existing CMOS technology. A basic building block of this scheme is the probabilistic bit (P-Bit), which utilizes a novel device such as a stochastic magnetic tunnel junction (sMTJ) to generate tunable randomness by nature. This work presents the first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit, capable of generating rail-to-rail stochastic output with a mere collection of 3 transistors + 1 sMTJ. Furthermore, simulations also confirm this P-Bit's functionality in probabilistic logic circuits. The demonstration of such P-Bit paves the way towards realizing monolithic large-scale probabilistic computing architecture on CMOS chips.