SHIELD: A Segmented Hierarchical Memory Architecture for Energy-Efficient LLM Inference on Edge NPUs
This work addresses energy efficiency for LLM inference on resource-constrained edge devices, representing an incremental improvement by optimizing refresh for specific activation types.
The paper tackled the problem of high energy consumption from periodic refresh of embedded DRAM (eDRAM) used for storing activations in LLM inference on edge NPUs, by proposing SHIELD, a segmented hierarchical memory architecture that reduces eDRAM refresh energy by 35% while maintaining accuracy on benchmarks like WikiText-2, PIQA, and ARC-Easy.
Large Language Model (LLM) inference on edge Neural Processing Units (NPUs) is fundamentally constrained by limited on-chip memory capacity. Although high-density embedded DRAM (eDRAM) is attractive for storing activation workspaces, its periodic refresh consumes substantial energy. Prior work has primarily focused on reducing off-chip traffic or optimizing refresh for persistent Key-Value (KV) caches, while transient and error-resilient Query and Attention Output (QO) activations are largely overlooked. We propose SHIELD, a lifecycle-aware segmented eDRAM architecture that jointly exploits temporal residency and bit-level sensitivity in bfloat16 (BF16) activations. SHIELD isolates the sign and exponent fields from the mantissa, disables refresh for transient QO mantissas, and applies relaxed refresh to persistent KV mantissas. Across multiple LLMs and inference scenarios, SHIELD reduces eDRAM refresh energy by 35% relative to a standard-refresh baseline while preserving accuracy on WikiText-2, PIQA, and ARC-Easy.