Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic Computing
For researchers and engineers in neuromorphic computing, this work highlights a critical bottleneck that could limit the scalability and efficiency of digital neuromorphic systems.
This paper reveals that on-chip memory in digital neuromorphic processors, including SRAM and STT-MRAM, has become a major consumer of area and energy, creating a new memory wall that may hinder their competitiveness in edge and embedded applications.
The rapid advancement of neuromorphic technology aims to address the memory wall challenge inherent in conventional von Neumann architectures. This paper critically examines current digital neuromorphic processors and their strategies to mitigate this bottleneck. While designed to bring computation closer to memory through distributed architectures, our findings indicate that on-chip memory systems, including SRAM and emerging technologies like STT-MRAM, have become significant consumers of area and energy, leading to a new memory wall. Through an analysis of energy and area efficiency in various memory technologies, we argue that without a re-evaluation of memory organization, digital neuromorphic processors may struggle to compete effectively in edge and embedded applications. We conclude with potential pathways for future research to overcome the limitations of on-chip memory in neuromorphic systems.