Programmable Packet Scheduling with Dynamic Reordering at Line Rate
This work addresses the limitation of existing programmable scheduling models (PIFO, PIEO) that cannot support dynamic-ordering algorithms like pFabric, enabling more expressive scheduling for high-speed networks.
UIFO introduces a two-level abstraction over classes and packets to enable dynamic reordering of buffered packets in programmable switch scheduling, achieving 100 Gbps line-rate throughput on FPGA and ASIC implementations.
High-speed switch packet scheduling demands both line-rate performance and programmability. Existing programmable hardware scheduling models, such as PIFO and PIEO, can express a broad range of scheduling algorithms; however, their semantics are restricted to packet-level ordering and cannot dynamically reorder buffered packets, which limits the support for dynamic-ordering algorithms such as pFabric. To overcome this limitation, we propose UIFO (Update-In-First-Out), a new programmable scheduling model that introduces a two-level abstraction over classes and packets. UIFO enables dynamic updates to the scheduling order at the class level while preserving in-order packet scheduling within each class, thereby supporting dynamic reordering of already-buffered packets. Furthermore, UIFO remains fully compatible with and generalizes existing PIFO and PIEO models. We implement a hardware prototype of UIFO based on priority-queue designs and evaluate it on an FPGA platform and in a 28 nm ASIC process. Overall, UIFO significantly enhances scheduling expressiveness and maintains favorable scalability while sustaining 100 Gbps line-rate throughput.