CMOS-integrated superparamagnetic tunnel junction-based p-bit
For researchers in probabilistic computing, this solves the integration bottleneck of sMTJs with CMOS, enabling scalable hardware for combinatorial optimization and machine learning.
This work demonstrates the first CMOS-integrated superparamagnetic tunnel junction (sMTJ)-based probabilistic bit (p-bit), showing that sMTJ resistance fluctuations can generate a tunable digital output voltage. This establishes feasibility for scalable probabilistic computing hardware.
Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.