Toward designing workload-aware Surface Code Architectures
This work addresses architectural overhead challenges in fault-tolerant quantum computing for quantum advantage applications, representing an incremental improvement over prior designs.
The paper tackles the trade-off between logical-qubit accessibility and density in fault-tolerant quantum computing architectures by proposing a workload-aware design that balances these objectives, resulting in up to 21% reduction in data tiles and near-optimal cycles per instruction.
Practical quantum advantage is expected to depend on fault-tolerant quantum computing, although the architectural overhead needed to support fault tolerance is still extremely high. Prior FTQC designs generally emphasize either fast logical-qubit accessibility at the cost of significant qubit overhead, or high logical-qubit density at the cost of added workload latency. We propose an architecture that balances these competing objectives by placing surface-code patches around an ancilla-centric region, which yields nearly uniform ancilla access for all data qubits. Building on this design, we introduce a new workload-driven placement method that uses the $T$-gate profile of an application to determine an effective floorplan. We further provide a reconfigurable optimization for reducing the latency of $Y$-gate measurements on a per-workload basis. To improve flexibility, we also study concurrent execution of multiple programs on the same architecture. Numerical evaluation indicates that our approach keeps cycles per instruction near the optimal regime while reducing the number of required data tiles by up to $\sim21\%$, and achieves up to $\sim90\%$ efficiency when running 10 programs concurrently.