Transient Multiscale Workflow for Thermal Analysis of 3DHI Chip Stack
It addresses the challenge of accurate 3D transient thermal simulation including BEOL structures for chip designers, but the demonstration is limited to a single RVE and the workflow is based on prior work.
The paper presents a transient thermal workflow for 3D heterogeneous structures in BEOL, generating property maps for a 1 mm by 1 mm SoC-style die with 100x100 grids (5 μm RVEs) and 50x50 grids (10 μm RVEs), and demonstrating transient effective conductivity for a single RVE.
Modern package designs make use of technologies such as backside power delivery (BSPD) and 3D stacked chiplets that require accounting for the heterogeneity in back end of the line (BEOL) structures in hot-spot prediction. Multiscale homogenization strategies have been demonstrated to be effective for steady-state simulations, however accurate 3D transient simulations that include BEOL structures remain an open challenge. In this work, we demonstrate a transient thermal workflow that accounts for the 3D heterogeneous structures in the BEOL for problems with strong- and weak- temporal scale separation under the assumption of temperature independent constitutive properties. Our workflow, based on Bloomfield et. al. 2025, automatically extracts, meshes, and homogenizes thermal properties from GDSII and OASIS files to construct thermal property maps. Property maps (heat capacity and conductivity) have been generated for a 1 mm by 1 mm SoC-style model die that was constructed with LibreLane for 100 by 100 grids with 5 micron by 5 micron representative volume elements (RVEs), and 50 by 50 grids with 10 micron by 10 micron RVEs. The expressions for a transient effective conductivity are provided and a demonstration of the impact of the transient effects are provided for a single RVE. Finally, transient conductivity maps have been provided for a time integration timestep of dt=0.001.