Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip
This work provides an energy-efficient, reconfigurable neuromorphic computing platform for machine learning tasks, bridging the gap between digital and analog systems without specialized hardware.
The authors propose a scalable neuromorphic architecture using clockless digital circuits on FPGAs, achieving competitive audio classification performance with significantly lower power consumption than traditional digital implementations.
We propose a scalable neuromorphic architecture based on spiking dynamics emerging from the autonomous time-continuous evolution of clockless (asynchronous) digital circuits. Implemented on commercially available field-programmable gate arrays (FPGAs), our system implements networks of interacting Boolean spiking neurons with configurable excitatory and inhibitory synaptic weights. A complete processing pipeline enables efficient handling of spike-encoded data for solving machine-learning tasks. We demonstrate competitive performance for an audio classification task with spike-based encoding and high-speed processing. Power consumption is significantly lower than traditional digital implementations; this makes our approach an efficient alternative that bridges the gap to dedicated analog neuromorphic systems without the need for specialized hardware design. More generally, our approach establishes clockless digital hardware as a viable platform for neuromorphic computing. It paves the way for reconfigurable chips to be turned into energy-efficient quasi-analog neuromorphic processors.