Code size reduction by advanced near addressing modes
For developers of real-time control systems using RISC-V, this work addresses the code size overhead caused by limited global pointer range, though it is an incremental extension of existing addressing modes from other architectures.
This paper proposes adding near addressing modes to the RISC-V ISA to reduce code size for real-time systems with many global variables, achieving significant code size reductions and performance improvements across representative workloads.
To enable debugging and calibration of real time systems, which are in interaction with the real plant, the software used on those systems often has a huge number of global variables. The huge number of global variables exceed the range addressable relative to the global pointer. Therefore, addressing these variables normally needs two instructions. Other CPU architectures commonly used in the real time control systems domain address these by various near addressing modes. This results in significant code size reductions and performance boost. This paper discusses different variants to add such near addressing features to the RISC-V ISA. The impact on the code size is evaluated with different representative workloads.