CLIPGen: A Chiplet Link IP Modeling and Generation Framework for 2.5D Architecture Exploration
System architects lack suitable tools for early 2.5D design space exploration; CLIPGen fills this gap by providing rapid, accurate estimates without requiring deep packaging expertise.
CLIPGen provides an automated framework for generating chiplet link IP with power, performance, and area estimates across various 2.5D packaging configurations, enabling early design space exploration. In a UCIe case study, it enables co-optimization of package and chiplet architecture.
Advanced 2.5D Systems-in-Package (SiPs) compose a growing portion of high-performance systems. While the packaging and interconnect choices play a large role in the overall system design, system architects still lack a suitable framework for early design space exploration which takes these choices into account. Current interconnect models fall mostly into the categories of 1) detailed models which are generally inflexible and require deep packaging expertise, or 2) high-level models which don't provide enough information to make accurate architectural design decisions. In this work, we present an automated chiplet IP generation framework which provides power, performance, and area estimates for various 2.5D packaging and communication configurations. The IP generator produces standard collaterals required for high-level simulation/estimation, RTL simulation, and place-and-route-level implementation (Verilog, Liberty, LEF, and datasheet). Using our framework, architects can co-optimize the package and chiplet architecture through rapid power, performance, and area estimates of various packaging strategies. As a case study, we examine generated UCIe interfaces across several packaging options.